1. Field of the Invention
The invention generally relates to computer systems, processors and corresponding operation methods, and in particular to techniques for processing interrupts.
2. Description of the Related Art
Generally, an interrupt can be described as an asynchronous event that suspends normal processing and temporarily diverts the flow of control through an “interrupt handler” routine. Interrupts may be caused by both hardware and software. Interrupt techniques are frequently used in many existing computer system technologies.
Referring to FIG. 1, the hardware components of a common computer system layout are depicted. It is to be noted that this figures shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard of FIG. 1 include the CPU (Central Processing Unit) 100, a northbridge 105, a southbridge 110, and system memory 115.
The northbridge 105 usually is a single chip in a core-logic chipset that connects the processor 100 to the system memory 115 and, e.g., to the AGP (Accelerated Graphic Port) and PCI (Peripheral Component Interface) buses. The PCI bus is commonly used in personal computers for providing a data path between the processor 100 and peripheral devices like video cards, sound cards, network interface cards and modems. The AGP bus is a high-speed graphic expansion bus that directly connects the display adapter and system memory 115. AGP operates independently of the PCI bus.
The southbridge 110 is usually the chip in a system core-logic chipset that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus, the USB (Universal Serial Bus), that provides plug-n-play support, controls the PCI-ISA (Industry Standard Architecture) bridge, manages the keyboard/mouse controller, provides power management features, and controls other peripherals.
In modern computer systems, two different kinds of interrupts can be distinguished: level sensitive interrupts (or level triggered interrupts) and edge triggered interrupts. Generally speaking, level sensitive interrupts can be viewed to define a condition for an interrupt whereas edge triggered interrupts can be viewed as a discrete event.
Standard PCI functions and devices use level sensitive interrupts. Level sensitive interrupts can be shared by multiple I/O devices, meaning that multiple I/O devices can share the same interrupt line even though individually the interrupts from each device are discrete events. That is, multiple devices can all assert the line, and when a level sensitive interrupt occurs, the ISR (Interrupt Service Routine) must poll all the devices that are sharing the interrupt line.
Edge triggered interrupts are handled differently from level sensitive interrupts because a single edge triggered interrupt counts as a single occurrence of an event while level sensitive interrupts are conditions that exist. Modern bus concepts use e.g., MSI (Message Signal Interrupt) transport mechanisms to reduce the number of sideband signals. Message signal interrupts are edge triggered.
A conventional technique for dealing with interrupts is specified in the APIC (Advanced Programmable Interrupt Controller) standard. It is used primarily in multiprocessor systems and supports interrupt redirection and interrupt transmission between processors.
Referring to FIG. 2, APIC consists of two parts at the system level. One part 250 resides in the I/O subsystem and is called I/O APIC. The other part is the so-called Local APIC 220 in the processor 200. The Local APIC 220 and the I/O APIC 250 communicate over a dedicated APIC bus 240. The I/O APIC bus interface consists of two bi-directional data signals and a clock signal.
The Local APIC unit 220 of the processor 200 contains the necessary intelligence to determine whether or not the processor 200 should accept interrupts broadcast on the APIC bus 240. The Local APIC 220 also provides local pending of interrupts, nesting and masking of interrupts, and handles all interactions with its local processor 200. The I/O APIC unit 250 consists of a set of interrupt input signals, an interrupt redirection table, programmable registers, and a message unit for sending and receiving APIC messages over the APIC bus 240. The I/O APIC unit 250 selects the corresponding entry in the redirection table and uses the information in that entry to format an interrupt request message. Each interrupt pin is individually programmable as either edge or level triggered.
FIG. 3 illustrates a conventional system configuration that uses APIC. As apparent from FIG. 3, the I/O APIC unit 330 is located in the southbridge device 320.
When a peripheral interrupt request occurs, the I/O APIC unit 330 sends an interrupt message to the processor 300. The WSC# (Write Snoop Complete) protocol forces the northbridge 310 and the processor 300 to snoop all posted writes, and provide a status indicator to the southbridge 320. The southbridge 320 (and the I/O APIC unit 330) is now free to issue a message to the processor 300 on the interrupt bus.
Another conventional approach is shown in FIG. 4. If a peripheral interrupt request occurs, the PIC (Programmable Interrupt Controller) 430 located in the southbridge 420 sends an interrupt request to the processor 400 on the INTR pin. The processor 400 then responds with an interrupt acknowledge cycle which forces the northbridge 410 to flush all posted writes.
In the conventional techniques, the general procedure is that the computer responds to an interrupt by storing the information about the current state of the running program, storing information to identify the source of the interrupt, and invoking a first-level interrupt handler. This first-level interrupt handler can discover the precise cause of the interrupt (e.g. if several devices share one interrupt) and what must be done to keep operating system tables (such as the process table) updated. This first-level handler may then call another handler, e.g. one associated with the particular device which generated the interrupt, i.e. a device driver.
However, the conventional techniques suffer from the additional communication necessary to identify the device which has experienced the interrupt event. That is, the drivers need to send a read request to access a register in the device, and the read information needs to be sent back to the driver. This may produce severe interrupt latencies. In particular where interrupts are shared by multiple devices, the drivers need to be successively activated so that each driver can check whether the interrupt event occurred at one of the devices that are associated to the respective driver. Due to the interrupt latency produced, the operating speed of the overall computer system may be significantly affected.